Architecture: Spring '04
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Question 1
Part A.
(i) one read/write port because you assume the future branches would be based on first branch if global history predictor. maybe k ports/simultaneous predictions if local history or non-history prediction, assuming retirement is also k-way.
(ii) 2k read, 1k write. Maybe 1 more write for loads that get serviced in the background. [depends on store uses literal offset or register,movc,etc]
(iii) k broadcast ports into issue queue, maybe extra for load, k from iq to FUs.
(iv) either k read and k write ports (1/1 per bank) or 1 port (with k instructions in one group, possible nops, fewer muxes)
Part B.
decode 1 if it's free, deallocate when retirement
Part C.
need multiple latches, need short cycles...muxes to resolve new and old values of register...complex, poor design, higher energy use...should not affect ipc. hot spot when all these registers accessed....longer branch mispredict penalty may decrease ipc.
Question 2
Part A. higher IPCs
- Larger-than-usual issue queue
- decreases clock rate, increases IPC
- Larger-than-usual ROB
- decreases clock rate, increases IPC
- Larger-than-usual physical registers
- decreases clock rate, increases IPC by decreasing the number of stalled instructions waiting for a rename
- Larger-than-usual BTB (or predictor structures)
- decreases clock rate (access delay), increases IPC by being able to predict more branches
- Longer-than-usual buses
- decrease clock rate, increases IPC by allowing the previous four improvements
Part B. instruction windows
(i) more instructions in flight: bigger issue -> dispatch bound means queue entries are wider + there are more of them -> bigger, slower issue queue. Plus data is copied more, rather than in and out of the register file once. Reduce complexity by passing addresses into the register file instead of the raw data. issue bound is better , probabely we don't need to store data is IQ in issue bound. (ii) keeping the registers separate is going to involve a lot more copying during the commit phase. If the registers are in one big file, commit can be done with about a single bit flip
Part C. issue queue organization
ROB?
