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==Problem 1== *Multithreding in hardware offers the promis of avoiding throughtput losses due data dependencies and branch mispredictions. The VLIW processors can also avoid thrughput losses due to dependencies and branching, by relying on the complier to handle dependencies and on static branch prediction and/or predicated execution hardware to handle brnahces, Consider now two possible processor designs that combine multithreading and the VLIW style as follows: * Design 1. The processor issues one VLIW instruction with K fields, packed with K instruction from same thread. Thread switching is performed on a cache miss or on encountering a branch instruction. * Design 2. The processor packs oeration from K different threads into K fields fo a single VLIW instruction. *(1) Sketch out the datapath details for both of there designs. Describe the instruction issuing, source operand accessing and instruction completion steps in each of there two desgns. How would you handle conditional brnach operation i Design2? *(2) What are the hardware requirement of these two designs? Give specific details about the register files (number of register files, number of read and write prots on each etc.). Be sure to clearly staty any assumptions that you make. *(3) compare the advantages and disavantages fo these two designs. *Keys: #*(1)Data Path: f1-f2-d1-d2-IQ-fu->ROB->RF. Conditional branch in design2 can be implemented as data dependicies. a GPR can be used to store the branch info and used to fetch next intruction. This will simplify the pipeline without increase the bubles. *(2)each thread has its own register set: a separate PC is also maintained fo reach thread in the fetch unit. The thread id or some equalivent information flows ito the FU with the thread instruction: this is used to select the appropriate register set for operand reads and result writes. need large insturction buffers. Each thread has its own buffer. #(3)The processing time per thread goes up, but the overal system/pipeline utilization goes up. ==Problem 2== *In modern processors, register renaming mechanisms are used to cope with data dependencies, while reorder buffer mechanisams are used bo provide precise interrupts. *(a) Sketch out the design of pipeline processor that integrate two mechanisms, where would you consider the register renaming scheme to be a good match for the reorder buffer mechanism? *(b)Brifly descibe the register renaming mechanism for your design: use one or a few sentences at most to describe what happens in each stage of your pipepline. *(c)How is the precise state resotred when an internal interrupt occurs? where consider the register renaming shceme to be a good match for the reorder buffer m ==Problem 3== ==Problem 4== ==Problem 5==

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